The present disclosure relates to computer systems having a function of synchronizing or desynchronizing the clock of a processor and the clock of a submodule, such as a bus, a memory, etc.
At present, many processors have a clock which is designed to be synchronized to the clock of a submodule, such as a bus, a memory, etc. In this case, the clock of the processor needs to be fixed to a frequency which is an integer multiple of the frequency of the clock of the submodule. Therefore, in some cases, the processor cannot operate at its maximum operating frequency. For example, when the maximum operating frequency of a processor is 350 MHz and the maximum operating frequency of a bus is 100 MHz, then if the clock of the processor is designed to be synchronized to the clock of the bus, the operating frequency of the processor needs to be set to 300 MHz. Also, when the frequency of a processor clock is decreased to reduce power consumption, then if the design for synchronization and the operating frequency of a bus are not changed, the frequency of the processor clock can be selected only from 100 MHz and 200 MHz, i.e., the clock frequency cannot be more finely selected (e.g., 250 MHz etc.).
There is a known asynchronous circuit design which solves such a problem. In the asynchronous circuit design, data is transferred between a processor and a submodule which are independent of and asynchronous to each other, and the clock frequency of one of the processor and the submodule does not need to be an integer multiple of the clock frequency of the other. Therefore, the processor and the submodule process data transfer therebetween while operating at independent clock cycles.
In a data transfer between the processor and the submodule using the asynchronous clocks, the latency increases due to measures for a metastable state compared to the design for synchronization. The increase of the latency may lead to a degradation in data transfer performance.
There is a known computer system having a synchronization/desynchronization controller which solves such a problem. According to this technique, when data is transferred between a processor and a submodule, the clock of the processor is momentarily synchronized to the clock of the submodule. After the completion of the data transfer, synchronization is disabled, and the processor clock operates asynchronously with respect to the submodule clock (see U.S. Pat. No. 5,794,019).